Design and implementation of real time video processor

This paper describes the design and implementation of an arithmetic unit for a video filter. The central unit of the video filter consists of six identical chips called Common Arithmetic Unit (CAU\´s), each of which contains three Common Arithmetic Cells (CAC\´s). These 64-pin CAU\´s are assembled on a board in a pipelined architecture to realize real time performance. The throughput rate for the chip is 11.3 Mhz. A constant time pipelined adder design has been proposed and implemented. The absolute delay is still . The area and absolute delay for our adder are within a constant factor of the optimal bounds.