DocumentCode
3010693
Title
On computing the detection probability of stuck-at faults in a combinational circuit
Author
Phillips, Benny P.
Author_Institution
Software Div., Tinker AFB, OK, USA
fYear
1991
fDate
24-26 Sep 1991
Firstpage
301
Lastpage
305
Abstract
In the context of random testing and testability analysis of combinatorial circuits, the author presents a reduced-search-space method for computing the exact detection probability of stuck-at faults. The proposed method is simple, search-oriented, and subexponential in the number of input variables of the circuit. A Prolog implementation is given
Keywords
automatic testing; combinatorial circuits; fault location; logic testing; probability; Prolog; combinational circuit; detection probability; random testing; reduced-search-space method; search oriented method; stuck-at faults; subexponential method; testability analysis; Circuit analysis; Circuit analysis computing; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Input variables; Probability distribution; Software testing;
fLanguage
English
Publisher
ieee
Conference_Titel
AUTOTESTCON '91. IEEE Systems Readiness Technology Conference. Improving Systems Effectiveness in the Changing Environment of the '90s, Conference Record.
Conference_Location
Anaheim, CA
Print_ISBN
0-87942-576-8
Type
conf
DOI
10.1109/AUTEST.1991.197566
Filename
197566
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