Efficient allocation method of multiport memories in ASIC data path synthesis

Recently multiport memory based design has become widely used, which provides a productive way for efficiently implementing large VLSI chips and is actually being used in very high speed RISC and superscalar processors. In this paper, Allocation of Multiport Memories in ASIC Datapath Synthesis (AMD), is presented to explore the design space for multiport memory allocation which minimizes the number of multiport memory modules and registers in each module according to the design constraints. The 0-1 integer Linear Program (ILP) model developed takes into account the the lifetime of registers. Experiments on benchmarks show encouraging results