Multi-valued Logic Addition and Multiplication in Galois Field

Author

Patel, V.K.S. ; Gurumurthy, K.S.

fYear

2009

fDate

28-29 Dec. 2009

Firstpage

752

Lastpage

755

Abstract

This paper presents addition and multiplication in Galois field using multi-valued logic. Multi-valued logic (MVL) has matured to the point where four-valued logic is now part of commercially available VLSI IC´s. Modulo-4 addition and multiplication is also presented in this paper. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.

Keywords

Galois fields; VLSI; logic design; logic gates; multivalued logic circuits; Galois field; Hspice; Karnaugh diagrams; VLSI; logic design; logic gates; modulo-4 addition; multivalued logic addition; multivalued logic multiplication; quaternary multiplier circuit; Capacitance; Delay; Galois fields; Geometry; Integrated circuit interconnections; Logic design; Logic devices; Multivalued logic; Power dissipation; Very large scale integration; Galois addition and multiplication; Modulo-n addition and multiplication; Multiple-valued logic; Quaternary logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT '09. International Conference on

Conference_Location

Trivandrum, Kerala

Print_ISBN

978-1-4244-5321-4

Electronic_ISBN

978-0-7695-3915-7

Type

conf

DOI

10.1109/ACT.2009.190

Filename

5375834