Title :
A radiation-hard 80 MHz phase locked loop for clock and data recovery
Author :
Toifl, Thomas ; Moreira, Paulo
Author_Institution :
Eur. Lab. for Particle Phys., CERN, Geneva, Switzerland
Abstract :
A radiation-hard phase locked loop (PLL) was developed to recover a low-jitter clock and data from an 80 MHz biphase mark encoded bitstream. The circuit was implemented in a 0.8 μm radiation-hard SOI-BiCMOS technology (DMILL) and operates with a power supply voltage of 3.3 V. After a 10 Mrad irradiation it showed no significant performance degradation. The circuit contains three innovative features: first, a parameter-independent biasing scheme, which adapts the charge-pump current to variations of transistor process parameters in order to achieve a predictable loop behavior. Second, a novel frequency detector, allowing the PLL to reach the target frequency without an external frequency reference, and third, a novel phase detector achieving direct lock to the incoming biphase mark signal
Keywords :
BiCMOS analogue integrated circuits; phase detectors; phase locked loops; radiation hardening (electronics); synchronisation; 0.8 micron; 10 Mrad; 3.3 V; 80 MHz; DMILL; PLL; SOI-BiCMOS technology; biphase mark encoded bitstream; charge-pump current; clock recovery; data recovery; direct lock; frequency detector; incoming biphase mark signal; loop behavior; low-jitter clock; parameter-independent biasing scheme; performance degradation; phase detector; phase locked loop; radiation-hard circuit; transistor process parameters; Circuits; Clocks; Delay; Detectors; Frequency; Large Hadron Collider; Phase detection; Phase locked loops; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780797
