A radiation-hard 80 MHz phase locked loop for clock and data recovery

A radiation-hard phase locked loop (PLL) was developed to recover a low-jitter clock and data from an 80 MHz biphase mark encoded bitstream. The circuit was implemented in a 0.8 μm radiation-hard SOI-BiCMOS technology (DMILL) and operates with a power supply voltage of 3.3 V. After a 10 Mrad irradiation it showed no significant performance degradation. The circuit contains three innovative features: first, a parameter-independent biasing scheme, which adapts the charge-pump current to variations of transistor process parameters in order to achieve a predictable loop behavior. Second, a novel frequency detector, allowing the PLL to reach the target frequency without an external frequency reference, and third, a novel phase detector achieving direct lock to the incoming biphase mark signal