DocumentCode :
3011746
Title :
A novel hardware algorithm for real-time image recognition based on real AdaBoost classification
Author :
Aoki, Takashi ; Hosoya, Eiichi ; Otsuka, Takuya ; Onozawa, Akira
Author_Institution :
NTT Microsystem Integration Laboratories, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa, 243-0198 Japan
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
1119
Lastpage :
1122
Abstract :
Real-time object detection is important for surveillance applications. This paper describes a high-performance object detector using a commercially available FPGA. Major bottlenecks in the real AdaBoost classifier are resolved. A new FIR-filter-like hardware architecture takes advantage of an FPGA´s hardware parallelism and block-RAM structure. The resulting design uses Xilinx Virtex 5 and achieves the real-time processing performance of 220 f/s at 201 MHz and adjustable recognition performance with a variable number of weak classifiers. This is the first demonstration of a histogram of oriented gradients and Real AdaBoost detector on an FPGA.
Keywords :
Classification algorithms; Computer architecture; Feature extraction; Field programmable gate arrays; Registers; Streaming media; Support vector machine classification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6271427
Filename :
6271427
Link To Document :
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