Title :
A low power monolithic subsampled phase-locked loop architecture for wireless transceivers
Author :
Hafez, Amr N. ; Elmasry, M.I.
Author_Institution :
VLSI Res. Group, Waterloo Univ., Ont., Canada
Abstract :
A subsampling stage driven by a crystal reference eliminates the prescaler and greatly reduces the division ratio of the PLL. The wide bandwidth of the loop inhibits the VCO phase-noise, allowing for the use of on-chip VCOs. The resulting architecture is particularly suitable for DDS-driven PLL architectures since it relaxes the requirements on the DDS thus further reducing the power consumption. The advantages of the architecture are highlighted and system- and circuit-level simulations are presented
Keywords :
CMOS integrated circuits; circuit feedback; integrated circuit noise; low-power electronics; phase locked loops; phase noise; transceivers; voltage-controlled oscillators; DDS-driven PLL architectures; VCO phase-noise inhibition; crystal reference; division ratio reduction; low power monolithic PLL architecture; onchip VCOs; power consumption reduction; subsampled phase-locked loop architecture; subsampling stage; wireless transceivers; Bandwidth; Channel spacing; Energy consumption; Frequency conversion; Interference; Phase locked loops; Phase noise; Transceivers; Voltage-controlled oscillators; Wireless sensor networks;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780808
