• DocumentCode
    3012072
  • Title

    A 250 mV bit-line swing scheme for a 1 V 4 Gb DRAM

  • Author

    Inaba, T. ; Takashima, D. ; Oowaki, Y. ; Ozaki, T. ; Watanabe, S. ; Ohuchi, K.

  • Author_Institution
    ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
  • fYear
    1995
  • fDate
    8-10 June 1995
  • Firstpage
    99
  • Lastpage
    100
  • Abstract
    We have proposed a new 1/4 Vcc bit-line swing architecture and related sense amplifier for 1 V 4 Gb DRAM and beyond. These schemes reduce power dissipation to 40% without degradation of the read-out signal and also improve device reliability.
  • Keywords
    DRAM chips; MOS memory circuits; integrated circuit reliability; 1 V; 250 mV; 4 Gbit; Gb DRAM; bit-line swing architecture; device reliability improvement; dynamic RAM; power dissipation reduction; sense amplifier; Capacitors; Flip-flops; Laboratories; MOSFET circuits; Operational amplifiers; Power dissipation; Random access memory; Stress; Threshold voltage; Variable structure systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    0-7800-2599-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.1995.520704
  • Filename
    520704
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3012072