Performance Analysis of Dual Vt Asymmetric SRAM - Effect of Process Induced Vt Variations

This paper examines the read stability, write ability and leakage power of various dual-Vt configurations, of an asymmetric SRAM cell (pass cell) in an array considering the process-induced intra-die threshold voltage variations using N-curve metrics. The effects of process induced Vt variations in 22 different dual-Vt cell combinations are evaluated and compared using Monte Carlo simulations. The comparisons are made with the help of power noise margins and leakage power. The variances and percentage variances from the mean of voltage and current margins for all 22 combinations are estimated and compared. The results help in process variation tolerant design of pass cell.