Evaluation of pipelined banyan switch architectures for ATM networks

In the pipeline banyan (PB) the reservation cycle in the control plane is made several times faster than payload transmission in data plane. This enables pipelining of multiple banyans. It is observed that the service rate is relatively low in the PB due to the banyan. For this, we present a scalable pipelined ATM switch employing a family of dilated banyan (DB) networks. A DB can be engineered between two extremes: (1) a low-cost banyan with internal and external conflicts; or (2) a high-cost conflict-free fully-connected network with multiple outlets. Increasing the dilation degree reduces path conflicts, which produces noticeable increase in service rate due to increase in throughput and decrease in path delay. Simulation of PDB was carried out under uniform traffic and simulated ATM traffic. We study performance under variation in the load, buffer size, and number of data planes. We show that performance of the switch is not degradable under ATM traffic with temporal and spatial burstiness generated by using the ON-OFF traffic model. A 256-input PDB can deliver up to 3.3 times the service rate of the PB with linear increase in hardware cost