Post-silicon skew tuning algorithm utilizing setup and hold timing tests

This paper treats post-silicon skew tuning for improving performance yield under various delay variations, and proposes a novel PDE tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of delay measurements. Our algorithm is based on “trial-and-error” approach, and it has a proper level of robustness against the variation of each PDE characteristics. As far as we know, this is the first systematic tuning algorithm whose termination is guaranteed for all chips including malfunctioning chips that have no feasible PDE setting. Simulation results show us that our tuning algorithm achieves yield improvement by around 50 points in percentage, while the loss (our algorithm fails to find a feasible PDE setting while the circuit has it (proven by ILP exact solution)) is kept up to 15 percent.