Digital background calibration of redundant split-flash ADC in 45nm CMOS

This paper presents a redundant flash ADC using a “Split-ADC” calibration structure and lookup-table-based correction. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed in the background in the digital domain. This 5.8 ENOB flash ADC is designed for a sampling rate of 1Gs/s in 45nm SOI CMOS.