A 286 mm/sup 2/ 256 Mb DRAM with X32 both-ends DQ

Author

Watanabe, Y. ; Wong, H. ; Kirihata, T. ; Kato, D. ; DeBrosse, J. ; Hara, T. ; Yoshida, M. ; Mukai, H. ; Quader, K. ; Nagai, T. ; Poechmueller, P. ; Pfefferl, K. ; Wordeman, M. ; Fujii, S.

Author_Institution

Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

1995

fDate

8-10 June 1995

Firstpage

105

Lastpage

106

Abstract

The growing market for high performance PCs has created a demand for a new generation of DRAMs with wide bit organization. A wider I/O DRAM is necessary to provide a sufficiently small granularity for the memory system. Hierarchical data-line architectures which transfer many bits over the memory array could potentially be used to provide a wide I/O. However, even using these schemes, chip size must expand to accommodate additional devices and wiring as the I/O width increases. This paper describes a chip architecture which minimizes the die size of wide I/O DRAMs and its application to a 256 Mb DRAM with X32 organization.

Keywords

CMOS memory circuits; DRAM chips; 0.25 micron; 256 Mbit; Mb DRAM; chip architecture; dynamic RAM; hierarchical data-line architectures; memory array; split global address bus; wide I/O DRAMs; wide bit organization; Added delay; CMOS technology; Capacitance; Circuit simulation; Random access memory; Semiconductor device measurement; Very large scale integration; Voltage; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7800-2599-0

Type

conf

DOI

10.1109/VLSIC.1995.520707

Filename

520707