A redundant decimal floating-point adder

Decimal floating-point addition is important for financial and business applications. There has been a growing interest in implementing decimal floating-point adders in hardware to enhance the speed of the decimal floating-point operations. In this paper, a redundant decimal floating-point adder is proposed with the ultimate objective of enhancing the speed of the decimal floating-point addition. Redundancy allows for a carry-free addition hence the addition process does not depend on the width of the operands. The results show that our design outperforms the conventional design in both the Decimal64 and the Decimal128 IEEE format.