DocumentCode
3012837
Title
Algorithm and architecture for on-line decimal powering computation
Author
Hassan, Mahmoud Y. ; ElDeeb, Tarek ; Fahmy, Hossam A H
Author_Institution
SilMinds, Maadi, Helwan, Egypt
fYear
2010
fDate
7-10 Nov. 2010
Firstpage
1158
Lastpage
1162
Abstract
An architecture for the computation of a decimal powering function is presented in this paper. The algorithm consists of a sequence of overlapped operations: 1) digit recurrence logarithm, 2) sequential multiplication, and 3) on-line antilogarithm. A correction scheme is introduced between the overlapped operations to guarantee correct on-line calculations. Execution times are estimated for decimal64 and decimal128 formats of the IEEE 754-2008 standard for floating point arithmetic.
Keywords
floating point arithmetic; sequential estimation; telecommunication standards; IEEE 754-2008 standard; correction scheme; decimal powering function; decimal128; decimal64; digit recurrence logarithm; floating point arithmetic; on-line antilogarithm; on-line decimal powering computation; sequential multiplication; Approximation methods; Computer architecture; Digital arithmetic; Error analysis; Hardware; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
978-1-4244-9722-5
Type
conf
DOI
10.1109/ACSSC.2010.5757586
Filename
5757586
Link To Document