• DocumentCode
    3012900
  • Title

    A new 3-phase design exploration methodology for video processor design

  • Author

    Lo, Wing-Yee ; Lun, Daniel P.K. ; Siu, Wan-chi

  • Author_Institution
    Centre for Signal Processing, Department of Electronic and Information Engineering, The Hong Kong Polytechnic University, Hong Kong
  • fYear
    2012
  • fDate
    20-23 May 2012
  • Firstpage
    1331
  • Lastpage
    1334
  • Abstract
    When making video processor design, conventional design exploration methodologies take extremely long time in parameter optimization but the final design may not necessarily meet the application requirements since the architecture cannot deviate too much from the initial design. To speed up the design process, statistical performance models were used to guide the simulation; however their accuracy is questionable. In this paper, a new 3-phase design exploration methodology for video processor is proposed. It makes use of an almost cycle-accurate performance model to provide information for refining the processor architecture. It can derive the optimal architecture in a much shorter period of time than the conventional methods. We successfully implemented a few video coding/decoding applications on the video processor derived from the proposed methodology. Simulation results show that it outperforms other video processors in both cost and performance perspectives.
  • Keywords
    Decoding; Design methodology; Logic gates; Pipelines; Software; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
  • Conference_Location
    Seoul, Korea (South)
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4673-0218-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.2012.6271487
  • Filename
    6271487