Title :
A novel power-off mode for a battery-backup DRAM
Author :
Takashima, D. ; Oowaki, Y. ; Watanabe, S. ; Ohuchi, K.
Author_Institution :
ULSI Res. Labs., Toshiba Corp., Kawasaki, Japan
Abstract :
A new DRAM whose power source can be shut off to achieve zero standby current was proposed and demonstrated. The measured maximum power-off time of 1 s of the 64 kb DRAM test device was as long as the measured maximum data retention time of the conventional DRAM, and the average standby current including the power-on current was 1/30 compared with the conventional one.
Keywords :
CMOS memory circuits; DRAM chips; 1 s; 64 kbit; battery-backup DRAM; dynamic RAM; poweroff mode; zero standby current; Capacitance; Circuit testing; Clocks; Laboratories; MOS devices; Power measurement; Random access memory; Research and development; Time measurement; Voltage;
Conference_Titel :
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7800-2599-0
DOI :
10.1109/VLSIC.1995.520709
