A low noise 32 bit-wide 256 M synchronous DRAM with column-decoded I/O line

Author

Lee, Seung-Jun ; Park, Kee-Woo ; Chung, Chang-Ho ; Son, Jin-Seung ; Park, Ki-Hong ; Shin, Sang-Ho ; Kim, Seok-Tae ; Han, Jeong-Dong ; Yoo, Hoi-Jun ; Min, Wi-Sik ; Oh, Kye-Hwan

Author_Institution

Hyundai Electron. Inc., Ichon-Kun, South Korea

fYear

1995

fDate

8-10 June 1995

Firstpage

113

Lastpage

114

Abstract

A 32 bit-wide 256 M synchronous DRAM (SDRAM) has been developed. The major design effort has been focused on minimizing the operating current at high clock frequencies to suppress power-line bouncing. The key techniques are split-bank architecture, multiplexed global address-bus with local column address counter, column-decoded data-line, and global data-bus architecture with reduced voltage swing. Simulation shows the reduction in the operating current at 200 MHz is up to 35% compared with a conventional scheme.

Keywords

CMOS memory circuits; DRAM chips; integrated circuit noise; 200 MHz; 256 Mbit; 32 bit; column-decoded I/O line; global data-bus architecture; high clock frequencies; local column address counter; low noise dynamic RAM; multiplexed global address-bus; operating current reduction; power-line bouncing suppression; split-bank architecture; synchronous DRAM; twin-well CMOS process; Artificial intelligence; Bandwidth; Clocks; Counting circuits; Frequency; Pulse amplifiers; SDRAM; Surges; Voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

0-7800-2599-0

Type

conf

DOI

10.1109/VLSIC.1995.520711

Filename

520711