A simulation-based study for DRAM power reduction strategies in GPGPUs

General Purpose Graphics Processing Units (GPGPUs) operate many threads concurrently, however they demand large DRAM access because of small internal memory size assigned to each thread. As a result, the power consumption in DRAM components becomes increasingly significant. We have examined a few techniques that can reduce DRAM power consumption in GPGPUs. A GPGPU simulator supporting L2 cache is used for this study. The effects of changing the memory channel organization, DRAM clock frequency, row buffer management policy, open or closed, and the L2 cache memory system are studied. Not only the total DRAM energy consumption but also that due to each DRAM operation, such as active-precharge, burst, and background, are estimated. The examined DRAM power reduction techniques bring negligible execution time changes for solving compute-bound problems, but they result in 12–27% savings of DRAM power consumption.