DocumentCode :
3013029
Title :
A cryogenic single electron transistor readout circuit: Practical issues and measurement considerations
Author :
Das, Kushal ; Lehmann, Torsten
Author_Institution :
School of Electrical and Telecommunications, The University of New South Wales, Sydney, Australia - 2052
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
1359
Lastpage :
1362
Abstract :
This paper revisits the design of a low power, fast CMOS Single Electron Transistor (SET) readout circuit which can operate at 4.2K and successfully detect 200pA SET signal current with µs detection speed. The design is revised in terms of increased transconductance and charge injection, reduced matching and drain-source resistance and other nonlinearities of the transistor behavior at low temperature. We have reviewed recent developments in cryogenic circuit design and low temperature measurement results found in literature since our previously reported work and used the acquired knowledge to validate our design formulation. We also incorporated possible non-idealities that may arise during the actual low temperature measurement of the fabricated chip. These effects are important since the readout IC requires pA and µV range compliance in order to interface with the SET and also talk to the external lab equipments via long cables.
Keywords :
CMOS integrated circuits; Cryogenics; Integrated circuit modeling; Mirrors; Noise; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6271494
Filename :
6271494
Link To Document :
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