A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme

For the node chips of wireless sensor networks (WSN), low power and fast settling are the two most important factors. In this paper, a low-power fast-settling phase-locked loop (PLL) frequency synthesizer working at 1.72 GHz∼1.74 GHz is designed for a 100 kb/s gauss frequency shift keying (GFSK) WSN transceiver. Low power consumption is realized by a bond-wire voltage-controlled oscillator (VCO) and a multi-stage power-scaling prescaler. Instead of conventional diode-based electro-static discharge (ESD) protection, resistor-based ESD protection is proposed for the bond-wire VCO to decrease the parasitic capacitance so that the automatic frequency calibration (AFC) range is enlarged by 50%. In addition, a dynamic-bandwidth scheme is proposed to meet the requirements of time-division half-duplex WSN systems. The chip is implemented with HJTC 0.18 µm CMOS technology. Measured results show that the PLL consumes 10.6 mW and settles within 18 µs including the AFC process; the phase noise is −91.9 dBc/Hz@10 kHz and −119.3 dBc/Hz@1 MHz under the receiving (Rx) state, and −95.2 dBc/Hz@10 kHz and −116.8 dBc/Hz@1 MHz under the transmitting (Tx) state.