CMOS implementation of a fast 4-2 compressor for parallel accumulations

This paper discusses about the design of a novel and fast 4-2 compressor. To enhance the speed performance, some changes are performed in the truth table of conventional 4-2 compressor which leaded to reduction of gate level delay to 2 XOR logic gates plus 1 transistor for all parameters. Because of similar paths, there will be no need for extra buffers in low latency paths to equalize the delays. Therefore, the power dissipation will be decreased and the output waveforms will be free of any glitch. The delay of proposed architecture is 340ps which is simulated by HSPICE using TSMC 0.35µm CMOS technology.