A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications

A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 µm CMOS process with an area of 1.69 mm² at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of −17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is −7.8 dBm, and the total double-side band noise figure is 13.2 dB.