Synthesis of circuits derived from decision diagrams-combining small delay and testability

We present a synthesis for testability approach to obtain EXOR-based circuits with inherently small delay. The starting point of our approach is a functional specification given in form of a so-called Kronecker Functional Decision Diagram (KFDD). The KFDD is transformed into a circuit by using a composition method based on Boolean matrix multiplication. Efficient algorithms working on the KFDD are applied during synthesis to avoid the creation of constant lines. Thereby first stuck-at fault testability is guaranteed by construction. Moreover tests for all faults can be derived efficiently from the graph of the KFDD. Thus, it is not necessary to apply automatic test pattern generation (ATPG) to compute test sets for the synthesized circuits or to check for redundancies. Area and delay of the circuits can be further improved by merging of equivalent gates. Altogether our approach makes it possible to combine high speed with fill testability for circuits derived from KFDDs. Finally, the efficiency of the proposed methods is demonstrated by experiments.