Title :
A simple keeper topology to reduce delay variations in nanometer domino logic
Author :
Alioto, Massimo ; Palumbo, Gaetano ; Pennisi, Melita
Author_Institution :
DII - Università di Siena, Italy
Abstract :
In this paper, a simple topology to reduce delay variations in domino logic gates is discussed. According to a previous analysis by the same authors, the feedback loop implemented by the keeper transistor and the output inverter gate is responsible for a delay variability increase, compared to static CMOS logic. The proposed strategy reduces the loop gain associated with this feedback loop, and hence its impact on delay variations. As a result, delay variations associated with the keeper insertion are lowered by approximately 50%, with no penalty in area, noise margin and nominal performance.
Keywords :
Delay; Inverters; Logic gates; Noise; Standards; Topology; Transistors;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271554