DocumentCode
3014122
Title
A methodology for design verification
Author
Hu, Eileen ; Yeh, Bill ; Chan, Thomas
Author_Institution
Apple Comput. Inc., Santa Clara, CA, USA
fYear
1994
fDate
19-23 Sep 1994
Firstpage
236
Lastpage
239
Abstract
Recent advancements in design automation tools have helped to shorten the design time for many ASICs. The functional verification of these ASICs, however, remains a wholly labor intensive and sequential task. This paper documents a parallel flow methodology that addresses the problem with a different approach to resource distribution for verification. Such a distribution allows for more time and resources to be dedicated to the verification task while still supporting a shortened design cycle
Keywords
application specific integrated circuits; circuit analysis computing; hardware description languages; logic CAD; ASICs; CAE tools; HDL; RTL; design automation tools; design time; design verification; functional verification; parallel flow methodology; resource distribution; shortened design cycle; verification task; Application specific integrated circuits; Computer aided engineering; Design automation; Design engineering; Design methodology; Design optimization; Hardware design languages; Resource management; Software tools; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-2020-4
Type
conf
DOI
10.1109/ASIC.1994.404568
Filename
404568
Link To Document