DocumentCode
3014308
Title
A low-power bipolar circuit for Gbit/s LSIs-current mirror control logic (CMCL)
Author
Kishine, K. ; Ichino, H.
Author_Institution
NTT LSI Labs., Kanagawa, Japan
fYear
1995
fDate
8-10 June 1995
Firstpage
127
Lastpage
128
Abstract
A low-power bipolar circuit for Gbit/s LSIs, Current Mirror Control Logic (CMCL), is proposed. To reduce supply voltage, the lower differential pairs of ECL series-gate circuits are replaced by current mirror circuits. This CMCL circuit achieves 3.1-Gbit/s (D-F/F) and 4.3-GHz (T-F/F) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(F/F).
Keywords
bipolar logic circuits; current-mode logic; emitter-coupled logic; large scale integration; 1.8 mW; 2.0 V; 3.1 Gbit/s; 4.3 GHz; CMCL; D-F/F; ECL; T-F/F; current mirror control logic; high-speed LSIs; low-power bipolar circuit; High speed optical techniques; Laboratories; Large scale integration; Latches; Logic circuits; Mirrors; Power dissipation; Power supplies; Utility programs; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
0-7800-2599-0
Type
conf
DOI
10.1109/VLSIC.1995.520718
Filename
520718
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