Title :
A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture
Author :
Zhu, Hongbo ; Shibata, Tadashi
Author_Institution :
VLSI Design and Education Center (VDEC), The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, 113-8656, Japan
Abstract :
A VLSI image processor capable of extracting motion features from moving images in real time has been developed employing row-parallel and pixel-parallel architectures based on the digital pixel sensor (DPS) technology. Directional edge filtering of input images is carried out in row-parallel processing to minimize the chip real estate. To achieve a real-time response of the system, a fully pixel-parallel architecture has been explored in adaptive binarization of filtered images for essential feature extraction as well as in their temporal integration and derivative operations. As a result, self-speed-adaptive motion-feature-extraction has been established. The chip was designed and fabricated in a 65-nm CMOS technology and used to build an object detection system. Motion-sensitive target image localization was demonstrated as an illustrative example.
Keywords :
Adders; Arrays; Feature extraction; Image edge detection; Random access memory; Sorting; Very large scale integration;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271563