A simple method for relating time- and frequency-domain measures of oscillator performance

This paper presents a simple technique for linking time domain (jitter) and frequency domain (phase noise) measures of oscillator performance. The key concept is the definition of a single figure-of-merit in the time- or frequency-domain that relates system-level performance (such as jitter or phase noise) to circuit-level parameters (such as power dissipation and signal amplitude). This technique is particularly applicable to circuit- and system-level design of voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs). The technique allows VCO and PLL design and characterization to take place in the domain (time or frequency, PLL open-loop or closed-loop) that provides the most insight into sources of jitter, while allowing a direct link to system-level performance as measured in any other domain. The methodology also speeds simulation since only the open loop VCO need be simulated, which allows a substantial savings in simulation time. Design examples and experimental results are presented for existing PLLs showing good agreement to the theoretical predictions