An output tracking delay-recycled clock skew-compensation and/or duty-cycle-correction circuit

A clock skew-compensation and/or duty-cycle correction circuit (CSADC) is indispensably required to maximize the performance of synchronous double edge triggered systems. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more power consumption and design complexity. A compact delay-recycled CSADC is proposed in this work. Compared to conventional output feedback tracking CSADC, the proposed circuit achieves a 24.3 times reduction in power, a 2.9 times reduction in lock-in cycles, and a 169.2 times reduction in power-to-bandwidth ratio. Furthermore, even compared to conventional open loop CSADCs, the proposed circuit still achieves at least a 2.81 times reduction in power and a 5.47 times reduction in power-to-bandwidth ratio.