Title :
Efficient charge recovery logic
Author :
Moon, Yong ; Jeong, Deog-Kyoon
Author_Institution :
Dept. of Electron. Eng., Seoul Nat. Univ., South Korea
Abstract :
Efficient Charge Recovery Logic (ECRL) is proposed as a candidate for low-energy adiabatic logic. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows 4-6 times power range with a practical loading and operation frequency range. Circuits are designed using 1.0 /spl mu/m CMOS technology with a reduced threshold voltage of 0.2 V.
Keywords :
CMOS logic circuits; adders; carry logic; integrated circuit design; logic gates; pipeline arithmetic; 0.2 V; 1.0 micron; CMOS technology; ECRL; carry lookahead adder; efficient charge recovery logic; inverter chain; low-energy adiabatic logic; operation frequency range.; pipelined structure; power range; threshold voltage; throughput; Adders; CMOS logic circuits; CMOS technology; Clocks; Inverters; Logic circuits; Power supplies; Semiconductor diodes; Threshold voltage; Throughput;
Conference_Titel :
VLSI Circuits, 1995. Digest of Technical Papers., 1995 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
0-7800-2599-0
DOI :
10.1109/VLSIC.1995.520719
