Title :
A chip-to-chip clock-deskewing circuit for 3-D ICs
Author :
Chuang, Ai-Jia ; Lee, Yu ; Yang, Ching-Yuan
Author_Institution :
Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan
Abstract :
A clock-deskewing circuit (CDC) using a dual delay-locked-loop technique is presented. The CDC can synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. Simulated in a 0.18µm CMOS technology, the maximum operating frequency is 1.5 GHz and the cycle-to-cycle clock jitter is 7.74 ps. Total power dissipation of the CDC is 56mW under a 1.8-V supply.
Keywords :
CMOS integrated circuits; Clocks; Delay; Jitter; Synchronization; Through-silicon vias; Wires;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271574
