A chip-to-chip clock-deskewing circuit for 3-D ICs

A clock-deskewing circuit (CDC) using a dual delay-locked-loop technique is presented. The CDC can synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. Simulated in a 0.18µm CMOS technology, the maximum operating frequency is 1.5 GHz and the cycle-to-cycle clock jitter is 7.74 ps. Total power dissipation of the CDC is 56mW under a 1.8-V supply.