General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL

Author

Zanchi, A. ; Bonfanti, A. ; Levantino, S. ; Samori, C.

Author_Institution

Data Converter Products, Texas Instrum. Inc., Dallas, TX, USA

fYear

2001

fDate

2001

Firstpage

32

Lastpage

37

Abstract

In this work we derive a general formula to link the phase noise rated via the cycle-to-cycle jitter of the oscillation period, to the single sideband to carrier ratio (SSCR). The validity of the relationship between the time- and frequency-domain figures of merit has been first tested through the simulation of a widely popular case: the phase noise spectrum featured by PLL synthesizers. As a further proof, measurements have also been performed on CMOS and bipolar integrated VCOs and PLLs, by adopting time-to-amplitude conversion techniques

Keywords

frequency synthesizers; frequency-domain analysis; jitter; phase locked loops; phase noise; time-domain analysis; voltage-controlled oscillators; PLL synthesizers; PLLs; SSCR; VCOs; cycle-to-cycle jitter relationship; frequency-domain figures of merit; oscillation period; phase noise; single sideband to carrier ratio; time-domain figures of merit; time-to-amplitude conversion techniques; Bandwidth; Circuit simulation; Circuit stability; Frequency; Instruments; Jitter; Phase locked loops; Phase noise; Synthesizers; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on

Conference_Location

Austin, TX

Print_ISBN

0-7803-6742-1

Type

conf

DOI

10.1109/SSMSD.2001.914933

Filename

914933