General SSCR vs. cycle-to-cycle jitter relationship with application to the phase noise in PLL

In this work we derive a general formula to link the phase noise rated via the cycle-to-cycle jitter of the oscillation period, to the single sideband to carrier ratio (SSCR). The validity of the relationship between the time- and frequency-domain figures of merit has been first tested through the simulation of a widely popular case: the phase noise spectrum featured by PLL synthesizers. As a further proof, measurements have also been performed on CMOS and bipolar integrated VCOs and PLLs, by adopting time-to-amplitude conversion techniques