Title :
Gate recognition and netlist reduction for switch-level simulation of dynamic bit-level systolic arrays
Author :
Blotti, A. ; Mannozzi, F. ; Roncella, R. ; Saletti, R. ; Tinfena, F.
Author_Institution :
Dipt. di Ingegneria dell´´Inf.: Elettronica, Inf., Telecomunicazioni, Pisa Univ., Italy
Abstract :
A program for gate recognition has been developed and used to reduce the netlist produced by layout flat extraction of a 1.2 million transistor bit-level systolic array design. The pipeline dynamic flip-flops as well as other elemental structures typical of systolic arrays are recognized. The netlist was reduced by a factor 8, thus allowing a post-layout switch-level simulation of the whole chip, otherwise impossible on the original netlist
Keywords :
circuit layout CAD; flip-flops; logic CAD; pipeline processing; systolic arrays; dynamic bit-level systolic arrays; gate recognition; layout flat extraction; netlist reduction; pipeline dynamic flip-flops; post-layout switch-level simulation; Application specific integrated circuits; Circuit simulation; Data mining; Data structures; Databases; Flip-flops; Pipelines; Registers; Switches; Systolic arrays;
Conference_Titel :
Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-6742-1
DOI :
10.1109/SSMSD.2001.914937
