Title :
Is there a tradeoff between programmability and performance?
Author :
Halstead, Robert ; Villarreal, Jason ; Moussalli, Roger ; Najjar, Walid
Author_Institution :
Univ. of California, Riverside, CA, USA
Abstract :
While the computational power of Field Programmable Gate Arrays (FPGA) makes them attractive as code accelerators, the lack of high-level language programming tools is a major obstacle to their wider use. Graphics Processing Units (GPUs), on the other hand, have benefitted from advanced and widely used high-level programming tools. This paper evaluates the performance, throughput and energy of both FPGAs and GPUs on image processing codes using high-level language programming tools for both.
Keywords :
computer graphic equipment; coprocessors; field programmable gate arrays; image coding; FPGA; GPU; code accelerators; field programmable gate arrays; graphic processing units; high-level language programming tools; image processing codes; programmability-performance tradeoff; Benchmark testing; Field programmable gate arrays; Graphics processing unit; Hardware; Kernel; Pixel; Programming;
Conference_Titel :
Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4244-9722-5
DOI :
10.1109/ACSSC.2010.5757683
