Noise analysis of monolithic RF balanced down conversion mixers

Author

Li, Li ; Tenhunen, Hannu

Author_Institution

Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden

fYear

2001

fDate

2001

Firstpage

70

Lastpage

75

Abstract

In this paper, noise features of monolithic RF balanced down conversion mixers are examined and analysed in detail with a periodic steady state simulator. The three kinds of port matching circuit architecture are proposed. Applying these optimum architectures to the single and double balanced down conversion (SBDC and DBDC) mixers can largely improve the mixers´ performance. The valuable reference parameters were given in order to design low noise, low power consumption and high performance mixers. The validated mixers were designed by using a 25 GHz Si bipolar technology, which is under 2.7 V power supply, RF at 5.8 GHz, and IF at 100 MHz and 1 GHz, respectively. The conversion gain is better than 0 dB. The noise figure is lower 10 dB

Keywords

MMIC mixers; bipolar MMIC; circuit simulation; elemental semiconductors; impedance matching; integrated circuit design; integrated circuit noise; low-power electronics; silicon; 10 dB; 100 MHz to 5.8 GHz; 2.7 V; 25 GHz; RF balanced down conversion mixers; Si; Si bipolar technology; double balanced mixers; high performance mixers; low noise operation; low power consumption; monolithic mixers; noise analysis; optimum architectures; periodic steady state simulator; port matching circuit architecture; single balanced mixers; Analytical models; Circuit noise; Circuit simulation; Circuit topology; Impedance matching; Mixers; Noise figure; Noise measurement; Radio frequency; Steady-state;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on

Conference_Location

Austin, TX

Print_ISBN

0-7803-6742-1

Type

conf

DOI

10.1109/SSMSD.2001.914940

Filename

914940