A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system

Author

Gerosa, Andrea ; Bernardini, Riccardo ; Pietri, Stefano

Author_Institution

Dipartimento di Elettronica e Inf., Padova Univ., Italy

fYear

2001

fDate

2001

Firstpage

87

Lastpage

92

Abstract

This work proposes a fully integrated random numbers generator. A chaotic system has been chosen as a source of randomness, in order to grant statistical independence and uniform distribution to the 8-bit generated words. An effective and compact architecture, based on a pipeline ADC only, has been singled out and realized in a standard 0.8 μm CMOS process. Particularly main circuit non-idealities have been properly managed, in order to enhance the statistical properties of the generated numbers. The randomness has been proved and quantified by post-layout simulations. Finally the circuit occupies 2.2 mm² of silicon area and dissipates 50 mW when clocked at 20 MHz

Keywords

CMOS integrated circuits; analogue-digital conversion; chaos generators; mixed analogue-digital integrated circuits; pipeline processing; random number generation; 0.8 micron; 20 MHz; 50 mW; 8 bit; ASIC; CMOS process; chaotic system; circuit nonidealities; compact architecture; fully integrated implementation; pipeline ADC; post-layout simulations; random numbers generator; statistical independence; uniform distribution; Analog-digital conversion; CMOS process; Chaos; Chaotic communication; Circuit simulation; Clocks; Pipelines; Quantization; Random number generation; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on

Conference_Location

Austin, TX

Print_ISBN

0-7803-6742-1

Type

conf

DOI

10.1109/SSMSD.2001.914944

Filename

914944