An improved analysis and design methodology for RF Class-E power amplifiers with finite DC-feed inductance and switch On-resistance

Previous analytical efforts to incorporate the impact of finite switch ON-resistance into the design procedure of Class-E power amplifiers (PAs) have imposed one or both of the so-called “Class-E switching conditions”, namely zero voltage switching (ZVS) and zero derivative of voltage at switching (ZDVS). These are essential for high efficiency operation only in the absence of losses. In this work, more general design equations have been derived without imposition of either ZVS or ZDVS. The optimal design is found to exhibit neither ZVS nor ZDVS, thereby validating the analysis. For the first time, an attempt has been made to incorporate the input power into the analysis, which facilitates optimization of power-added efficiency (PAE). The resulting designs exhibit better performance in terms of output power and PAE compared to existing design approaches. The analytical results have been verified through Spectre-RF simulations at 5GHz in 0.18µm and 65nm CMOS. Through this design procedure, we further demonstrate that Class-E PAs at 5GHz based on thick-oxide devices in 0.18µm CMOS, despite their lower speed, outperform those based on 65nm CMOS devices due to their higher voltage-handling capability.