DocumentCode :
3015059
Title :
Modified shuffled schedule for nonbinary low-density parity-check codes
Author :
Lin, Jun ; Yan, Zhiyuan
Author_Institution :
Department of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA 18015, USA
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
1767
Lastpage :
1770
Abstract :
In this paper, a shuffled schedule of the Min-Max decoding algorithm is proposed for nonbinary LDPC codes. To reduce the latency and memory requirement, a modified shuffled schedule with much simpler check node processing is also proposed, based on a new shuffle sort algorithm. Numerical simulations for three LDPC codes over GF(32) with different lengths and rates show: (1) both the shuffled and modified shuffled schedule converge faster and have slightly better error performance than the flooding schedule, and (2) the degradation of the modified shuffled schedule in error performance as well as convergence rate is negligible.
Keywords :
Convergence; Decoding; Degradation; Memory management; Parity check codes; Schedules; Signal to noise ratio;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul, Korea (South)
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6271606
Filename :
6271606
Link To Document :
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