Automated power supply noise reduction via optimized distributed capacitors insertion

Phenomena like IR drop, L dI/dt, electromigration and crosstalk are menacing in increasing proportions ultra deep submicron ICs functionality. This is a consequence of their growing complexity driven by increased speed, size, and interconnect density due to technology scaling down and high metal levels number used. The related consequences are delays, errors and failures, and depend on the global number, position and connections among gates. The correct approach to face the solution of these problems must be global and not local to a single gate. Having such a global prospect is easy at the end of a design flow, but leads to an expensive trial and error methodology: an alternative is facing early in the design sequence the potential noise generation of a circuit block. This paper focuses on a power supply model such as each gate connected to the power busses has an integrated capacitor automatically generated to reduce simultaneous switching noise. This model has been inserted in a developing tool for interconnect parameters prediction and noise safety design