• DocumentCode
    3015295
  • Title

    Study on the optimal distribution of redundancy effort in cross-layer reliable architectures

  • Author

    Aymerich, N. ; Rubio, Albert

  • Author_Institution
    Electron. Eng. Dept., High-Performance Integrated Circuits & Syst. Design Group, Univ. Politec. de Catalunya (UPC), Barcelona, Spain
  • fYear
    2013
  • fDate
    5-8 Aug. 2013
  • Firstpage
    245
  • Lastpage
    249
  • Abstract
    This paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with an ever-increasing number of components. Moreover, future technology generations are expected to have associated lower levels of quality. For these reasons, it is emerging nowadays a renewed interest in the development of reliable architectures. In this work we delve into this topic putting special emphasis on the system hardware hierarchy. We analyze the advantages in terms of reliability of distributing redundancy effort in cross-layer systems. We base our analysis on a general fault model that takes into account both devices and interconnections. Using the Rent´s Law we relate the number of devices and interconnections for different configurations of redundancy and compare the global error probability. Our results provide meaningful information about the benefits that can be achieved by properly choosing the system layer at which to apply redundancy, and if applicable, the optimal distribution of redundancy effort through the system layers.
  • Keywords
    computer architecture; error statistics; fault tolerant computing; multiprocessor interconnection networks; redundancy; reliability; Rent Law; computing systems; cross-layer reliable architectures; cross-layer systems; general fault model; global error probability; multiple-layer hierarchical systems; optimal redundancy effort distribution; redundancy techniques; system hardware hierarchy; Analytical models; Computer architecture; Error probability; Integrated circuit interconnections; Redundancy; Tunneling magnetoresistance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology (IEEE-NANO), 2013 13th IEEE Conference on
  • Conference_Location
    Beijing
  • ISSN
    1944-9399
  • Print_ISBN
    978-1-4799-0675-8
  • Type

    conf

  • DOI
    10.1109/NANO.2013.6720848
  • Filename
    6720848