Title :
Wafer fabrication ion implant charging-impact on gate oxide breakdown
Author :
Yeoh, Teong-San ; Hu, Shze-Jer
Author_Institution :
Intel Technol. Sdn. Bhd., Penang, Malaysia
Abstract :
Process induced charging is not new in the wafer fabrication process. However, it is difficult to identify as test structures used cannot detect this problem effectively, as these structures are not connected to large metal or polysilicon networks for charge collection, or if these structures are covered by thick photoresist. Ion implantation is a major process where charging poses a problem to the extent of transistor gate oxide breakdown or degradation. This is presented along with the respective charging models for these phenomena. This breakdown is strongly influenced by device design layout, implanter energy and diffusion breakdown strengths
Keywords :
dielectric thin films; electric breakdown; electric strength; integrated circuit layout; integrated circuit yield; ion implantation; photoresists; semiconductor process modelling; surface charging; charging models; device design layout; diffusion breakdown strength; gate oxide breakdown; implanter energy; ion implantation; metal charge collection networks; photoresist; polysilicon charge collection networks; process induced charging; test structures; transistor gate oxide breakdown; transistor gate oxide degradation; wafer fabrication ion implant charging; wafer fabrication process; Electric breakdown; Electrons; Fabrication; Implants; Insulation; Ion implantation; Physics; Resists; Space charge; Surface charging;
Conference_Titel :
Semiconductor Electronics, 1998. Proceedings. ICSE '98. 1998 IEEE International Conference on
Conference_Location :
Bangi
Print_ISBN :
0-7803-4971-7
DOI :
10.1109/SMELEC.1998.781153