Analysis of propagation delay in 3 - D stacked DRAM

Rapidly growing complexity in 3D ICs has led an increase in popularity of test methodologies based on delay testing. In this paper, we analyze the physical level design of 3-D stacked DRAM ICs with Through Silicon Via (TSV) to evaluate the propagation delay. We have performed design and electrical circuit model extraction to analyze the propagation delay in 3D DRAM ICs using the traditional 3-transistor model with 0.35nm CMOS technology. Simulation results are presented to show the accuracy and efficiency in determining the propagation delay in 3D DRAM ICs using the electrical circuit model proposed in this paper. We represent the propagation delay in TSVs by representing the RC time constant and the capacitive delay in DRAM cell load driver during pull up and pull down in CMOS. We have performed TDR and eye diagram analysis to validate our models. The proposed propagation delay model can be used for various high speed, high density memory.