A new approach for TCP/IP offload engine implementation in embedded systems

Author

Hashimoto, Koji ; Moshnyaga, Vasily G.

Author_Institution

Dept. of Electron. Eng. & Comput. Sci., Fukuoka Univ., Fukuoka, Japan

fYear

2010

fDate

7-10 Nov. 2010

Firstpage

1249

Lastpage

1253

Abstract

TCP/IP offload engine (TOE) is an essential technology to increase throughput of network connection. In this paper we present a novel approach for TOE implementation in embedded system with very stringent requirements on area and power. Our approach is based on two design optimizations. The first one deals with architectural enhancement for reducing the size of memory buffers in TOE hardware. The second one optimizes the TCP/IP data flow in order to speculatively process the TCP/IP packet headers in parallel to DMA data transfers. Experiments show that the approach is very effective. A prototype design of TOE receiver operating at a very low (25 MHz) frequency can achieve 13.1 Mbs throughput while requiring only 57.5 K 2-input NAND logic gates for control logic.

Keywords

buffer storage; embedded systems; optimisation; transport protocols; DMA data transfer; NAND logic gate; TCP/IP data flow; TCP/IP offload engine; TCP/IP packet header; TOE hardware; embedded system; frequency 25 MHz; memory buffer; Engines; Hardware; IP networks; Protocols; Receivers; Registers; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the Forty Fourth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

978-1-4244-9722-5

Type

conf

DOI

10.1109/ACSSC.2010.5757731

Filename

5757731