A dynamically programmable radio processing MPSoC with hardware-based task management

We propose a programmable heterogeneous multi-processor system-on-chip (MPSoC) platform architecture for flexible radio processing that aims at striking a balance between performance (as provided by ASICs) and flexibility (as provided by SDR). Based on a novel hardware-oriented Virtual Flow Pipelining (VFP) framework, the key highlights of this solution are a simple task-level programming model for provisioning protocol flows, and the use of dedicated hardware-based OS-like support (VFP controllers) for run-time task management. We present a clustering-based MPSoC organization with distributed-shared VFP controllers and architectural support for message passing to address the scalability, hardware complexity, and performance tradeoffs. Performance evaluation demonstrates high utilization (70%+) of processing elements (PE) even for short tasks (120 cycles@200 MHz), which highlights the performance potential of the architecture when compared against traditional software controlled radio platforms. Also, a 802.11a-like OFDM transmitter has been implemented using the platform and single and multiple concurrent traffic flows at data rates of 6, 12 and 24 Mbps are executed. The achieved peak throughputs are 27, 51 and 88.5 Mbps respectively.