Title :
Using HYPER to teach datapath design techniques in an ASIC design course
Author_Institution :
Dept. of Electr. & Comput. Eng., Mississippi State Univ., MS, USA
Abstract :
HYPER is a high level synthesis tool available from UC Berkeley for real-time, datapath intensive architectures such as those found in digital signal processing and video imaging applications. We have used HYPER as an adjunct tool in our ASIC design course for illustrating area versus time versus power tradeoffs in datapath design. These design tradeoffs can be explored via HYPER´s wide range of transformation capabilities which include pipelining, retiming, constant multiplication expansion, time-loop unrolling and various algebraic law transformations
Keywords :
application specific integrated circuits; electronic engineering education; field programmable gate arrays; hardware description languages; high level synthesis; integrated circuit design; teaching; ASIC design course; FPGAs; HYPER; algebraic law transformations; constant multiplication expansion; datapath design techniques; design tradeoffs; digital CAD; digital signal processing; high level synthesis tool; pipelining; real-time datapath intensive architectures; retiming; time-loop unrolling; transformation capabilities; video imaging; Application software; Application specific integrated circuits; Clocks; Design automation; Design methodology; Digital signal processing; Finite impulse response filter; High level synthesis; Logic design; Pipeline processing;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404576
