Title :
Test resource partitioning: a design and test issue
Author :
Teixeira, J.P. ; Teixeira, I.M. ; Pereira, C.E. ; Dias, O.P. ; Semião, J.
Author_Institution :
IST, INESC, Lisbon, Portugal
Abstract :
Product development economics and specs drive the need for on chip embedded test functionality. However, optimal partitioning of test functionality between a tester and a SOC is a non-trivial task, which must be solved during the system analysis phase. Hence, at system level, a trade-off analysis must be performed, in order to evaluate the costs and benefits of different partitioning schemes. The purpose of this contribution is to present a methodology and tools, using the Object Oriented (OO) Paradigm and UML, and a set of architectural Quality Metrics (QMs), to analyze the impact of different TRP schemes on systems architecture. A 4-core SOC case study is presented to guide the discussion
Keywords :
application specific integrated circuits; integrated circuit testing; logic partitioning; object-oriented methods; product development; specification languages; Object Oriented Paradigm; SOC; TRP schemes; UML; architectural Quality Metrics; on chip embedded test functionality; partitioning schemes; product development economics; system analysis phase; test resource partitioning; Automatic control; Automation; Bandwidth; Binary search trees; Built-in self-test; Degradation; Object oriented modeling; Quality assessment; System analysis and design; System testing;
Conference_Titel :
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
Conference_Location :
Munich
Print_ISBN :
0-7695-0993-2
DOI :
10.1109/DATE.2001.914997
