• DocumentCode
    3015851
  • Title

    An efficient architecture model for systematic design of application-specific multiprocessor SoC

  • Author

    Baghdadi, Amer ; Lyonnard, Damien ; Zergainoh, Nacer-E ; Jerraya, Ahmed A.

  • Author_Institution
    TIMA Lab., Grenoble, France
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    55
  • Lastpage
    62
  • Abstract
    In this paper, we present a novel approach for the design of application specific multiprocessor systems-on chip. Our approach is based on a generic architecture model which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of applications. In addition, it allows one accelerate the design cycle. This paper focuses on the definition of the architecture model and the systematic design flow that can be automated. The feasibility and effectiveness of this approach are illustrated by two significant demonstration examples
  • Keywords
    application specific integrated circuits; hardware-software codesign; integrated circuit design; logic CAD; logic partitioning; multiprocessing systems; application-specific multiprocessor SoC; architecture model; design cycle; flexibility; generic architecture model; modularity; scalability; systematic design; systematic design flow; template; Acceleration; Assembly; Communication networks; Computer architecture; Hardware; Laboratories; Multiprocessing systems; Process design; Scalability; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
  • Conference_Location
    Munich
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-0993-2
  • Type

    conf

  • DOI
    10.1109/DATE.2001.915001
  • Filename
    915001