• DocumentCode
    3015877
  • Title

    A hardware sharing architecture of deblocking filter for VP8 and H.264/AVC video coding

  • Author

    Chou, Yu-Lin ; Wu, Chung-Bin

  • Author_Institution
    Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan
  • fYear
    2012
  • fDate
    20-23 May 2012
  • Firstpage
    1915
  • Lastpage
    1918
  • Abstract
    In this paper, a hardware sharing architecture to perform the multi-standard deblocking filter that support VP8 and H.264/AVC is proposed. First, a reorganization of deblocking filter is used to derive a common architecture suitable for H.264 and VP8. The proposed design is then reused for the whole filtering. Finally, to further reduce the computational complexity, highly sharing architecture is also presented. Moreover, the adopted hardware sharing architecture overall saves 36.7% of shifters, 64.5% of adders and 100% of multipliers. The overall PSNR drops less than 1.47% on the VP8 decoder for low complexity applications.
  • Keywords
    computational complexity; decoding; filtering theory; video coding; H.264/AVC video coding; VP8 decoder; computational complexity; hardware sharing architecture; multistandard deblocking filter; Complexity theory; Computer architecture; Filtering; Filtering algorithms; Hardware; PSNR; Video coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
  • Conference_Location
    Seoul
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4673-0218-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.2012.6271647
  • Filename
    6271647