A systematic approach in designing a complex system with VHDL

As the size and complexity of digital systems increase continuously, hardware description language (HDL) based design methodology is quickly becoming the main stream in today´s digital system design. Although many of the HDL-based design practices follow the bottom-up fashion, the real strength of HDL is that it facilitates the top-down design process where higher level design concepts can be described and verified without delving into implementation details. This paper describes a complex system design practice using VHDL where a multi-level top-down design approach was adopted